Field
This disclosure relates generally to memory devices and, more particularly to memory devices that combine volatile memory and NVM.
Related Art
One aspect of NVM is that it has slower write speeds than volatile memories, especially static random access memories. Also, NVMs typically have lifetimes limited by the number of program/erase cycles that they undergo. One approach to addressing these issues is to have the normal operations carried out using the SRAM and then, when powering down, storing the data that is to be retained in the NVM. When operations are to continue and power is present, the data stored in NVM is restored to the SRAM. Thus, normal operations are achieved with the SRAM with the attendant benefits thereof and the non-volatile function is present when power is removed. Efficient combining of the NVM and the SRAM is difficult due to the very different operating characteristics. Combining the NVM and SRAM into a single memory array is thus difficult. One example is that optimizing the program and erase functions may be in conflict with the SRAM operation. This is further complicated by the voltages that are required for program and erase are not needed for SRAM operation so that the transistors of the SRAM are preferably not made with the complicating high voltage considerations in mind.
Accordingly there is a need to provide further improvement in achieving combined volatile and non-volatile memories.